1. Field of the Invention
The invention relates to a semiconductor device manufacturing method, particularly, a method of manufacturing a semiconductor device having a nonvolatile semiconductor memory and a capacitor element.
2. Description of the Related Art
Electrically programmable and erasable read-only memories (hereafter, called EEPROM) have been widely used in the field of its application, for example, cellular phones or digital camera.
In the EEPROM, binary or multi-valued digital data can be stored according to accumulation or non-accumulation of a predetermined amount of electric charge in a floating gate, and read out by detecting conduction change in a channel region corresponding to the amount of electric charge. There are a split-gate type EEPROM and a stacked-gate type EEPROM.
FIG. 12 is a cross-sectional view showing a structure of a memory cell of the split-gate type EEPROM. A n+ drain region 102 and a n+ source region 103 are formed on a front surface of a P-type semiconductor substrate 101, keeping a predetermined distance from each other. A channel region 104 is formed between the n+ drain region 102 and the n+ source region 103. A floating gate 106 is formed on a part of the channel region 104 and a part of the source region 103 with a gate insulation film 105 therebetween. A thick silicon oxide film 107 is formed on the floating gate 106 by a selective oxidation method.
Furthermore, a tunnel insulation film 108 is formed covering a side surface of the floating gate 106 and a part of an upper surface of the thick silicon oxide film 107. A control gate 109 is formed on the tunnel insulation film 108 and a part of the channel region 104.
An operation of the memory cell having this structure is as follows. First, when digital data is written in, channel hot electrons are injected into the floating gate 106 though the gate insulation film 105 by applying predetermined potentials to the control gate 109 and the source region 103 (e.g., 0V to the P-type semiconductor substrate 101, 2V to the control gate 109, and 10V to the source region 103) and flowing a current in the channel region 104. The channel hot electrons injected into the floating gate 106 are held in the floating gate 106 as electric charge.
Since capacitor coupling of the floating gate 106 and the source region 103 is highly larger than capacitor coupling of the control gate 109 and the floating gate 106, the potential of the floating gate 106 increases by the potential applied to the source region 103, thereby improving injection efficiency of the channel hot electrons to the floating gate 106.
On the other hand, when the digital data stored in the memory cell is erased, the drain region 102 and the source region 103 are grounded and a predetermined potential (e.g., 13V) is applied to the control gate 109, thereby flowing a Fowler-Nordheim tunneling current in the tunnel insulation film 108 and taking out electrons accumulated in the floating gate 106 therefrom to the control gate 109. At this time, since a sharp edge 106a is formed in an end portion of the floating gate 106, electric field concentration occurs in this sharp edge 106a. Therefore, it is possible to flow the Fowler-Nordheim tunneling current with a relatively low control gate potential, and data erasing can be performed effectively.
Furthermore, when the data stored in the memory cell is read out, predetermine potentials (e.g., 2V) are applied to the control gate 109 and the drain region 102. Then, a channel current flows in response to the amount of charge of electrons accumulated in the floating gate 106. The data can be read out by detecting this current by a current sense amplifier.
In the described split-gate type EEPROM, programming and data erasing can be performed with high efficiency. However, for convenience of a manufacturing process, a positional relation between the control gate 109 and the floating gate 106 and a positional relation between the control gate 109 and the thick silicon oxide film 107 are not self-alignment, so that the memory cell has been required to be designed in consideration of mask shifts. Therefore, the memory cell of the split-gate type EEPROM has had limitation in miniaturization.
For solving this problem, a split-gate type EEPROM of a self-alignment type has developed. FIG. 13 is a cross-sectional view showing a memory cell of the split-gate type EEPROM of the self-alignment type. As shown in FIG. 13, a first memory cell MC1 and a second memory cell MC2 are disposed symmetrically with respect to a common source region 203 as a center.
A structure of the first memory cell MC1 is as follows (the second memory cell MC2 has the same structure). A n+ drain region 202 and a n+ source region 203 are formed on a front surface of a P-type semiconductor substrate 201, keeping a predetermined distance from each other. A channel region 204 is formed between the n+ drain region 202 and the n+ source region 203. A floating gate 206 is formed on a part of the channel region 204 and a part of the source region 203 with a gate insulation film 205 therebetween. A spacer film 207 made of silicon oxide is formed by self-alignment on this floating gate 206.
Furthermore, a tunnel insulation film 208 is formed covering a side surface and a part of an upper surface of the floating gate 206. A control gate 209 is formed by self-alignment on a sidewall of the spacer film 207. That is, the control gate 209 is disposed on the side wall of the spacer film 207 and on a part of the channel region 204.
An operation of the first memory cell MC1 is the same as that of the memory cell of the EEPROM of FIG. 12. The feature of the first memory cell MC1 and the second memory cell MC2 is that the control gate 209 is formed by self-alignment on the floating gate 206 and the spacer film 207, and the source line 210 is in contact with the source region 203 by self-alignment. In such a split-gate type EEPROM of the self-alignment type, the memory cell can be miniaturized more.
The described memory cell of the split-gate type EEPROM of the self-alignment type is described in the Japanese Patent No. 3481934 and the Japanese Patent Application Publication No. 2003-124361.
In recent years, high performance of a system LSI or a microprocessor has been realized by setting the EEPROM therein. In such a system LSI, a capacitor element for forming an analog circuit and so on has been required to be part of the system, besides the EEPROM.
However, when the EEPROM and the capacitor element are formed on the same semiconductor substrate, there occurs a problem that a manufacturing process becomes complex and a cost increases by an increase in the number of processes. Furthermore, the number of thermal treatment processes increases due to formation of the capacitor element, thereby degrading reliability of the capacitor element and changing characteristics of a memory cell, a MOS transistor, and so on.